Display device having a main writing and additional writing periods

ABSTRACT

According to one embodiment, a display device includes a display panel including a gate line, source lines, and switching elements connected to the gate line and the respective source lines. A gate driver selects the gate line. A source driver supplies an image signal to the source lines. The image signals can be supplied to pixel electrodes through the switching elements. A frame period includes a first scan period in which the gate line is selected, a first hold period subsequent to the first scan period, a second scan period in which the gate line is selected subsequent to the first hold period, and a second hold period subsequent to the second scan period. The first hold period is longer than the second hold period.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2015-006614, filed Jan. 16, 2015, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a display device.

BACKGROUND

A technique to reduce the frame frequency is known as a method forreducing the consumed power of liquid crystal displays. For example, thefollowing technique is suggested. A rest period in which all the scansignal lines are in a non-scan state is set between scan periods inwhich the screen is scanned. In the rest period, the operation of adriving circuit for driving a display portion is stopped.

On the other hand, when the frame frequency is reduced, the voltageretained by each pixel tends to change as time passes. Thus, in thedisplayed image, the difference in luminance may be easily recognized asa flicker because of the difference in potential between frames. In thismanner, the display quality may be degraded.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 schematically shows a structure of a display device according toan embodiment.

FIG. 2 schematically shows a cross-sectional surface of a display panelPNL shown in FIG. 1.

FIG. 3 shows an example of a timing chart for writing an image signal toeach pixel PX of an active area ACT.

FIG. 4 shows an example of a timing chart for writing an image signal tothe pixel PX comprising a pixel electrode PE1.

FIG. 5 shows another example of the timing chart for writing an imagesignal to the pixel PX comprising the pixel electrode PE1.

FIG. 6 shows another example of the timing chart for writing an imagesignal to the pixel PX comprising the pixel electrode PE1.

DETAILED DESCRIPTION

In general, according to one embodiment, the following display device isprovided. The display device comprises:

a display panel comprising including a gate line, a plurality of sourcelines intersecting with the gate line, and a plurality of switchingelements electrically connected to the gate line and the respectivesource lines; and

a driving portion including a gate driver which selects the gate line bysupplying a predetermined voltage to the gate line, and a source driverwhich supplies image signals to the source lines for each frame period,wherein

the image signals are supplied from the connected source lines to pixelelectrodes through the switching elements connected to the gate lineselected by the gate driver,

the frame period comprises a first scan period in which the gate line isselected by the gate driver, a first hold period subsequent to the firstscan period, a second scan period in which the gate line is selected bythe gate driver at least once subsequent to the first hold period, and asecond hold period subsequent to the second scan period, and

the first hold period is longer than the second hold period.

Embodiments will be described with reference to the accompanyingdrawings. The disclosure is merely an example. Proper changes whichmaintain the spirit of the invention and are easily conceivable by aperson of ordinary skill in the art are included in the scope of thepresent invention as a matter of course. To further clarify theexplanation, the drawings may exemplarily show the width, thickness,shape, etc., of each portion in comparison with the actual aspect.However, the drawings are merely examples and do not restrict theinterpretation of the present invention. In the specification anddrawings of this application, elements which fulfill a functionidentical with or similar to those in the already described drawings maybe denoted by the same reference numbers or symbols, and theiroverlapping detailed descriptions may be arbitrarily omitted.

In the following embodiments, a liquid crystal display device isdisclosed as an example of a display device. The liquid crystal displaydevice can be used for various types of devices such as a smartphone, atablet, a mobile phone, a personal computer, a television receiver, anin-car device and a games console. The main structures disclosed in theembodiments may be also applied to, for example, an auto-luminouslight-emitting display device comprising an organic electroluminescentdisplay element, etc., an electronic paper display device comprising anelectrophoretic element, a display device to whichmicro-electromechanical systems (MEMS) are applied, or a display deviceto which electrochromism is applied.

FIG. 1 schematically shows a structure of a display device according toan embodiment.

The display device comprises a display panel PNL of active matrix type,a driving portion which supplies a signal for displaying an image to thedisplay panel PNL, and a backlight unit BLT which illuminates thedisplay panel PNL.

As described later, the display panel PNL is a liquid crystal displaypanel in which a liquid crystal layer is retained between a pair ofsubstrates. The display panel PNL comprises an active area (displayarea) ACT which displays an image. The active area ACT includes aplurality of pixels PX arrayed in a matrix. In the active area ACT, thedisplay panel PNL comprises m gate lines GL (GL1 to GLm), n source linesSL (SL1 to SLn), etc., where m and n are positive integers. For example,the gate lines GL extend along a first direction X and are arranged in asecond direction Y. The source lines SL extend along the seconddirection Y and are arranged in the first direction X. The gate lines GLor the source lines SL may not be formed linearly. Each of the gatelines GL and the source lines SL may be partially bended. The gate linesGL and the source lines SL may partially branch off.

The driving portion comprises gate drivers GD, a source driver SD and acontrol circuit CNT. At least a part of the gate drivers GD and thesource driver SD is formed on the display panel PNL. The control circuitCNT is provided in a driving IC chip mounted on the display panel PNL, aflexible printed circuit board, etc.

The gate lines GL extend to the outside of the active area ACT and areelectrically connected to the gate drivers GD (GD1 and GD2). In theexample shown in the figure, odd-numbered gate lines GL are connected togate driver GD1. Even-numbered gate lines GL are connected to gatedriver GD2. The source lines SL extend to the outside of the active areaACT and are electrically connected to the source driver SD. Thestructures of the gate drivers GD and the source driver SD are notlimited to the example shown in the figure.

Each pixel PX comprises a switching element SW, a pixel electrode PE, acommon electrode CE, etc. The switching element SW is composed of, forexample, an re-channel thin-film transistor. The switching element SW iselectrically connected to the gate line GL and the source line SL. Thepixel electrode PE is electrically connected to the switching elementSW. The common electrode CE is provided so as to be common to the pixelelectrodes PE of a plurality of pixels PX. Capacitance is formed betweenthe common electrode CE and each pixel electrode PE and retains an imagesignal (voltage) which is necessary for display of the pixel PX.

In the example shown in the FIG. 1, the active area ACT is composed of mlines (m gate lines) arranged in the second direction Y. Each line iscomposed of n pixels PX arranged in the first direction X and iselectrically connected to the same gate line GL. Thus, each gate line GLintersects with n source lines SL. Each line comprises n switchingelements SW and n pixel electrodes PE. The switching elements SW areelectrically connected to one gate line GL and the respective sourcelines SL. The pixel electrodes PE are electrically connected to therespective switching elements SW. The connection relationship of thepixels PX in the active area ACT is not limited to the example shown inthe figure.

The control circuit CNT generates various types of signals which arenecessary to display an image in the active area ACT based on anexternal signal supplied from an external signal source, and outputs thesignals to the gate drivers GD and the source driver SD. The controlcircuit CNT applies a common potential (VCOM) to the common electrodeCE. The gate drivers GD supply a scan signal to each gate line GL. Thesource driver SD supplies an image signal to each source line SL. Basedon the scan signal supplied to each gate line GL, the switching elementsSW connected to the same gate line GL are made conductive. Thus, imagesignals from the source driver SD can be written to the pixels PX of oneline. When image signals are supplied to source lines SL in a statewhere the switching elements SW of one line are conductive, the imagesignals are supplied to the pixel electrodes PE via the switchingelements SW which are in a conductive state. As this way, in each of thepixels PE, an electrical field is formed in accordance with thedifference between the potential of the pixel electrode PE and thepotential of the common electrode CE. The direction of alignment ofliquid crystal molecules contained in the liquid crystal layer iscontrolled by the electrical field formed between the pixel electrode PEand the common electrode CE. The image signal written to each pixel PXis retained by the capacitance between the pixel electrode PE and thecommon electrode CE until the next image signal is written.

When an image such as a moving or still image is displayed in the activearea ACT, the driving portion supplies a scan signal to the gate linesGL in series for each frame period and supplies an image signal to thesource line SL. However, when a still image or a moving image having asmall movement is displayed in the active area ACT, the driving portionsupplies a scan signal to the gate lines GL and supplies an image signalto the source line SL with a frame frequency less than a normal framefrequency (intermittent driving). For example, when the normal framefrequency which is used when a moving image is displayed in the activearea ACT is 60 Hz, the driving portion allocates sixty frame periods toone second and writes an image signal to all the pixels PX of the activearea ACT in one frame period of 1/60 s. When the frame frequency whichis used in intermittent driving is 1 Hz, the driving portion allocatesone frame period to 1/60 s out of one second and writes an image signalto all the pixels PX of the active area ACT. At this time, each pixel PXretains the written image signal for the remaining 59/60 s. It ispossible to reduce the consumed power of the display device byperforming intermittent driving in which the frame frequency isdecreased.

Here, the explanation of the detailed structure of the display panel PNLis omitted. A structure compatible with a twisted nematic (TN) mode, anoptically compensated bend (OCB) mode, a vertically aligned (VA) mode,an in-plane switching (IPS) mode, a fringe-field switching (FFS) mode,etc., may be applied to the display panel PNL.

The display panel PNL may be structured as a transmissive panel whichdisplays an image by selectively transmitting light from the backlightunit BLT provided on the back side of the display panel PNL as shown inthe example of the figure. The display panel PNL may be structured as areflective panel which displays an image by selectively reflectingoutside light incident on the display panel PNL. The display panel PNLmay be structured as a semi-transmissive panel in which transmissive andreflective types are combined with each other.

Various forms are applicable to the backlight unit BLT. The explanationof the detailed structure is omitted.

FIG. 2 schematically shows a cross-sectional surface of the displaypanel PNL shown in FIG. 1. Here, as an example, a display panel PNL towhich an FFS mode is applied is explained.

The display panel PNL comprises an array substrate AR as a firstsubstrate, a counter-substrate CT as a second substrate, and a liquidcrystal layer LQ retained between the array substrate AR and thecounter-substrate CT.

The array substrate AR comprises a first insulating substrate 10, afirst insulating film 11, a common electrode CE, a second insulatingfilm 12, a pixel electrode PE, a first alignment film AL1, etc. In thefollowing explanation of the array substrate AR, the upper side refersto a side close to the counter-substrate CT.

The first insulating substrate 10 is formed of an insulating materialhaving a light transmission property such as a glass substrate or aresin substrate. The first insulating film 11 is formed on the firstinsulating substrate 10. For example, a gate line, a source line and aswitching element (not shown) are formed between the first insulatingsubstrate 10 and the first insulating film 11. The common electrode CEis formed on the first insulating film 11. The common electrode CE isformed of a conductive material which is transparent such as indium tinoxide (ITO) or indium zinc oxide (IZO). The common electrode CE iscovered by the second insulating film 12. The pixel electrode PE isformed on the second insulating film 12 and faces the common electrodeCE. A slit SLA is formed to the pixel electrode PE. The pixel electrodePE is formed of a conductive material which is transparent such as TIOor IZO. The first alignment film AL1 covers the pixel electrode PE andis also formed on the second insulating film 12. The first alignmentfilm AL1 is formed of a material showing horizontal alignment and isprovided on a surface of the array substrate AR in contact with theliquid crystal layer LQ.

The counter-substrate CT comprises a second insulating substrate 20, alight-shielding layer BM, color filters CF1 to CF3, an overcoat layerOC, a second alignment film AL2, etc. The second insulating substrate 20is formed of an insulating material having a light transmission propertysuch as a glass substrate or a resin substrate. The light-shieldinglayer BM is formed on an inner surface of the second insulatingsubstrate 20, facing the array substrate AR. The color filters CF1 toCF3 are formed on the inner surface of the second substrate 20. The endportions of the color filters CF1 to CF3 overlap the light-shieldinglayers BM. Each of the color filters CF1 to CF3 is formed of a resinmaterial dyed in a different color. The overcoat layer OC covers thecolor filters CF1 to CF3. The second alignment film AL2 covers theovercoat layer OC. The second alignment film AL2 is formed of a materialshowing horizontal alignment and is provided on a surface of thecounter-substrate CT in contact with the liquid crystal layer LQ.

The liquid crystal layer LQ is enclosed between the first alignment filmAL1 of the array substrate AR and the second alignment film AL2 of thecounter-substrate CT.

A first optical element OD1 including a first polarizer PL1 is attachedto the array substrate AR. A second optical element OD2 including asecond polarizer PL2 is attached to the counter-substrate CT. The firstoptical element OD1 and the second optical element OD2 may include otheroptical elements such as a retardation plate.

FIG. 3 shows an example of a timing chart for writing an image signal toeach pixel PX of the active area ACT.

V(GL1), V(GLm/2) and V(GLm) in the figure correspond to the scan signalssupplied to the gate line GL1, the gate line GLm/2 and the gate lineGLm, respectively. The gate line GL1 is located on the one end side ofthe active area ACT. The gate line GLm/2 is located in the middle partof the active area ACT. The gate line GLm is located on the other endside of the active area ACT. The figure shows that, when the pulse ishigh (H) in each scan signal, the switching elements connected to eachgate line are conductive. When the pulse is low (L), the switchingelements connected to each gate line are not conductive. In thefollowing explanation, the phrase “a gate line GL is selected” indicatesthat the switching elements connected to the gate line GL are madeconductive by the gate driver GD through supply of a high scan signal tothe gate line GL.

VS in the FIG. 3 corresponds to an image signal supplied to one sourceline SL. The image signal includes a first image signal I1, a secondimage signal I2 and a third image signal I3 as explained later. Thesource line SL intersects with the gate line GL1, the gate line GLm/2and the gate line GLm.

V(PE1), V(PEm/2) and V(PEm) in the FIG. 3 correspond to the absolutevalues of the differences in potential between the common electrode andthe pixel electrode PE1, the pixel electrode PEm/2 and the pixelelectrode PEm, respectively. The pixel electrode PE1 is electricallyconnected to the switching element connected to the gate line GL1 andthe source line SL. The pixel electrode PEm/2 is electrically connectedto the switching element connected to the gate line GLm/2 and the sourceline SL. The pixel electrode PEm is electrically connected to theswitching element connected to the gate line GLm and the source line SL.The present embodiment is explained below, including a case to which adriving method of inverting the polarity (in other words, a method ofdriving the liquid crystal layer with alternate current) for each frameis applied.

One frame period T includes a main write period W, a first rest periodR1, an additional write period WA and a second rest period R2. The restperiod may be called a hold period.

The main write period W is equivalent to a period in which the activearea ACT is scanned. In the main write period W, the first image signalI1 corresponding to the image which should be displayed essentially iswritten to all the pixels PX of the active area ACT. In the main writeperiod W, a scan signal is supplied in series from the gate drivers GDto m gate lines GL of the active area ACT. Thus, the switching elementsconnected to each gate line GL are made conductive. At this time, thefirst image signal I1 supplied to the source lines SL is supplied toeach pixel electrode via the switching elements. In the example shown inthe FIG. 3, at the time point when the pulse of the scan signal V(GL1)of the gate line GL1 rises, the first image signal I1 supplied to thesource line SL is supplied to the pixel electrode PE1. Subsequently, atthe time point when the pulse of the scan signal V(GLm/2) of the gateline GLm/2 rises, the first image signal I1 supplied to the source lineSL is supplied to the pixel electrode PEm/2. Subsequently, at the timepoint when the pulse of the scan signal V(GLm) of the gate line GLmrises, the first image signal I1 supplied to the source line SL issupplied to the pixel electrode PEm. In this manner, the first imagesignal I1 is written to each pixel PX. The first image signal I1 writtento each pixel PX is retained until the next image signal is written. Inthe example shown in the figure, the main write period W is equivalentto a period from the time point when the pulse of the scan signal V(GL1)of the gate line GL1 rises to the time point when the pulse of the scansignal V(GLm) of the gate line GLm falls.

The first rest period R1 subsequent to the main write period W is aperiod in which m gate lines GL of the active area ACT are in a non-scanstate concurrently. In the first rest period R1, an image signal is notwritten to any pixel PX of the active area ACT. Thus, in the first restperiod R1, each pixel PX retains the first image signal I1 which hasbeen written in the main write period W. In the example shown in theFIG. 3, the first rest period R1 is equivalent to a period from the timepoint when the pulse of the scan signal V(GLm) of the gate line GLmfalls in the main write period W to the time point when the pulse of thescan signal V(GL1) of the gate line GL1 rises in the additional writeperiod WA explained below.

The additional write period WA subsequent to the first rest period R1 isequivalent to a period in which the active area ACT is scanned. In theadditional write period WA, the second image signal I2 is additionallywritten to all the pixels PX of the active area ACT. The second imagesignal I2 which is additionally written is a signal corresponding to thefirst image signal I1, and may be the same image signal as the firstimage signal I1. The second image signal I2 may be a signal having avoltage less than that of the first image signal I1. The relationshipbetween the first image signal I1 and the second image signal I2 isexplained in detail later. In the additional write period WA, in amanner similar to that of the main write period W, a scan signal issupplied in series from the gate drivers GD to m gate lines GL of theactive area ACT. In this manner, the switching elements connected toeach gate line GL are made conductive. At this time, the second imagesignal I2 supplied to the source lines SL is supplied to each pixelelectrode via the switching elements. In the example shown in thefigure, at the time point when the pulse of the scan signal V(GL1) ofthe gate line GL1 rises, the second image signal I2 supplied to thesource line SL is supplied to the pixel electrode PE1. Subsequently, atthe time point when the pulse of the scan signal V(GLm/2) of the gateline GLm/2 rises, the second image signal I2 supplied to the source lineSL is supplied to the pixel electrode PEm/2. Subsequently, at the timepoint when the pulse of the scan signal V(GLm) of the gate line GLmrises, the second image signal I2 supplied to the source line SL issupplied to the pixel electrode PEm. In this manner, the second imagesignal I2 is written to each pixel PX. The second image signal I2written to each pixel PX is retained until the next image signal iswritten. In the example shown in the FIG. 3, the additional write periodWA is equivalent to a period from the time point when the pulse of thescan signal V(GL1) of the gate line GL1 rises to the time point when thepulse of the scan signal V(GLm) of the gate line GLm falls.

The second rest period R2 subsequent to the additional write period WAis a period in which m gate lines GL of the active area ACT are in anon-scan state concurrently. In the second rest period R2, an imagesignal is not written to any pixel PX of the active area ACT. Thus, inthe second rest period R2, each pixel PX retains the second image signalI2 which has been written in the additional write period WA. In theexample shown in the FIG. 3, the second rest period R2 is equivalent toa period from the time point when the pulse of the scan signal V(GLm) ofthe gate line GLm falls in the additional write period WA to the timepoint when the pulse of the scan signal V(GL1) of the gate line GL1rises in the main write period W of the next frame period describedbelow.

The main write period W of the next frame period is equivalent to aperiod in which the active area ACT is scanned. In the main write periodW of the next frame period, the third image signal I3 corresponding tothe image which should be displayed essentially is written to all thepixels PX of the active area ACT. The image signal I3 is an image signalcorresponding to the next frame of the image signal I1. However, when astill image is displayed, the third image signal I3 is a signalequivalent to the first image signal I1.

In one frame period T, a time which is equal to or longer than the mainwrite period W is allocated to the additional write period WA. Thelength of the additional write period WA is set in accordance with thenumber of times of additional writing. As shown in the example of theFIG. 3, when additional writing is performed once in the additionalwrite period WA (in other words, when all of m gate lines GL areselected once for each gate line GL), the length of the additional writeperiod WA is equal to that of the main write period W. In this case, forexample, each of the main write period W and the additional write periodWA is 1/60 s. When additional writing is performed a plurality of timesin the additional write period WA (in other words, when all of m gatelines GL are selected a plurality of times for each gate line GL), theadditional write period WA is longer than the main write period W. Forexample, when the number of times of additional writing is p (p is aninteger greater than or equal to two), the main write period W is 1/60 swhile the additional write period WA is p/60 s.

In one frame period T, a time which is longer than the main write periodW is allocated to the first rest period R1 and the second rest periodR2. The first rest period R1 is set longer than the second rest periodR2. Thus, the additional write period WA is started in the latter halfof the frame period T (in other words, started after the passage of atime longer than T/2 from the start of the main write period W).

In the example of the FIG. 3, when additional writing is not performedwithout setting the additional write period WA, the potential V(PE1) ofthe pixel electrode PE1 is decreased gradually over time as shown by thebroken line. Thus, a relatively large difference ΔV1 in potential isgenerated when the third image signal I3 equivalent to the first imagesignal I1 is supplied to the pixel electrode PE1 in the main writeperiod W of the next frame period. This phenomenon is also seen in thepotential of the other pixel electrodes. Thus, in the image displayed inthe active area ACT, the difference in luminance is easily recognized asa flicker because of the difference in potential between the frames ofthe pixels PX.

In the present embodiment, the second image signal I2 is additionallywritten in the additional write period WA. Therefore, the reduction inpotential of the first image signal I1 retained by each pixel isprevented, or the potential is restored to a level close to that of thepotential of the first image signal I1 which has been written in themain write period W. Thus, the difference ΔV2 in potential which isgenerated when the third image signal I3 equivalent to the first imagesignal I1 is written to each pixel PX in the main write period W of thenext frame period is less than the difference ΔV1 in potential. In thismanner, the difference in luminance of the displayed image is difficultto be recognized as a flicker.

In particular, this type of additional writing is preferably performedat a time point when the reduction in potential of the image signalretained by each pixel PX is dramatic. Since the potential of theretained image signal is decreased gradually as time passes, additionalwriting is preferably started in the latter half of one frame period T.In this manner, it is possible to further reduce the difference inpotential from the image signal written in the next frame period. Thus,the difference in luminance of the image can be further reduced.

Even when the frame frequency is reduced, the difference in luminance isdifficult to be recognized as a flicker in the displayed image. Thus, itis possible to reduce the consumed power and prevent the degradation ofthe display quality.

Even when the polarity of the third image signal I3 is different fromthat of the first image signal I1, by applying additional writing in aframe period, the difference in the absolute value is made small betweenthe potential of the image signal in the latter half of the frame periodand the potential of the image signal which is used when the mainwriting is performed in the next frame period. Thus, the difference inluminance between frames is reduced. In this manner, the flicker isdecreased.

When additional writing is performed a plurality of times for each pixelPX in the additional write period WA, the additional write period WA maybe started before the passage of T/2 from the start of a first scanperiod S1.

Now, this specification looks at a gate line (GL1) and the pixelelectrode (PE1) connected to the gate line (GL1) in the active area.

FIG. 4 shows an example of a timing chart for writing an image signal tothe pixel PX the having pixel electrode PE1.

One frame period T comprises the first scan period S1, a first holdperiod A, a second scan period S2 and a second hold period B.

The first scan period S1 is equivalent to a period in which an imagesignal corresponding to the image to be displayed essentially is writtento all the pixels PX electrically connected to the gate line GL1. In thefirst scan period S1 in which the gate line GL1 is selected by the gatedriver GD, the switching elements connected to the gate line GL1 aremade conductive, and an image signal is supplied to the pixel electrodePE1. The first scan period S1 is included in the above main write periodW. When the main write period W in which a scan signal is supplied inseries to m gate lines GL is 1/60 s, the first scan period S1 is lessthan or equal to (1/60)·(1/m) s. For example, the first scan period S1is the period from the time point when the pulse of the scan signalV(GL1) rises to the time point when the pulse falls, the peak time ofthe pulse of the scan signal V(GL1), or the period in which the pulse ofthe scan signal V(GL1) is greater than or equal to a threshold voltagefor making the switching elements connected to the gate line GL1conductive.

In the FIG. 4, a part of the scan signal V(GL1) is enlarged. Althoughthe form of the pulse is substantially rectangular in an example, thewaveform tends to bend until the pulse reaches the peak at the time ofrising, and until the pulse reaches the bottom at the time of falling.In this type of pulse waveform, the first scan period S1 can be definedas a period from the time point when the pulse waveform rises from thebottom rapidly to the time point when the pulse waveform falls from thepeak rapidly.

The first hold period A subsequent to the first scan period S1 isequivalent to a period in which the image signal written to each pixelPX is retained. The first hold period A includes the above first restperiod R1 and the period in which the other gate lines are selected inthe main write period W. For example, the first hold period A isequivalent to a period from the time point when the pulse of the scansignal V(GL1) falls in the first scan period S1 to the time point whenthe pulse of the scan signal V(GL1) rises in the second scan period S2described later.

The second scan period S2 subsequent to the first hold period A isequivalent to a period in which an image signal is additionally writtento all the pixels PX electrically connected to the gate line GL1. In thesecond scan period S2 in which the gate line GL1 is selected by the gatedriver GD, the switching elements connected to the gate line GL1 areconductive, and an image signal is supplied to the pixel electrode PE1.The second scan period S2 is included in the above additional writeperiod WA. In the second scan period S2, the gate line GL1 is selectableonce or more times. When the gate line GL1 is selected only once asexemplarily shown in the FIG. 4, the time can be defined in the samemanner as the above first scan period S1. When additional writing isperformed once in the second scan period S2 (in other words, when thegate line GL1 is selected once), the length of the second scan period S2is equal to that of the first scan period S1.

The second hold period B subsequent to the second scan period S2 isequivalent to a period in which the image signal written to each pixelPX is retained. The second hold period B includes the above second restperiod R2 and the period in which the other gate lines are selected inthe additional write period WA. For example, the second hold period B isequivalent to a period from the time point when the pulse of the scansignal V(GL1) falls in the second scan period S2 to the time point whenthe pulse of the scan signal V(GL1) rises in the next frame perioddescribed later.

The first scan period S1 of the next frame period is equivalent to aperiod in which an image signal corresponding to the image to bedisplayed essentially is written to all the pixels electricallyconnected to the gate line GL1.

In one frame period T, a time longer than the first scan period S1 andthe second scan period S2 is allocated to the first hold period A andthe second hold period B. The first hold period A is set longer than thesecond hold period B. In one frame period T, the second scan period S2is close to the next frame period.

As explained with reference to FIG. 3, the potential V(PE) of the pixelelectrode PE is reduced gradually over time. When the additional writingin the second scan period S2 is performed at a time point close to thenext frame period, the reduction in the potential V(PE) of the pixelelectrode PE is prevented. Thus, it is possible to reduce the differencein potential from the image signal written in the next frame period. Inthis manner, it is possible to prevent a flicker which is caused by thedifference in luminance in the displayed image and prevent thedegradation of the display quality.

The first hold period A is preferably set longer than the period T/2which is a half of one frame period T. In other words, the second scanperiod S2 is preferably started in the latter half of one frame periodT. Because of this setting, the reduction in the potential V(PE) of thepixel electrode PE can be effectively prevented.

Now, this specification explains the relationship between the imagesignal written in the first scan period S1 (equivalent to the abovefirst image signal I1) and the image signal written in the second scanperiod S2 (equivalent to the above second image signal I2).

When the difference in potential between the pixel electrode PE1 and thecommon electrode CE in the first scan period S1 (in other words, thepotential of the first image signal I1 written in the first scan periodS1) is V0, and the difference in potential between the pixel electrodePE1 and the common electrode CE at the time of the passage of the firsthold period A (in other words, the potential V(PE1) of the pixelelectrode PE1 at the time of the passage of the first hold period A) isV1, and the difference in potential between the pixel electrode PE1 andthe common electrode CE in the second scan period S2 (in other words,the potential of the second image signal I2 additionally written in thesecond scan period S2) is Va, the relationship V1<Va≦V0 is preferablysatisfied.

V1 can be predicted based on the frame frequency, the length of thefirst hold period A, the physical properties of the liquid crystalmaterial, etc. Va needs to be set higher than V1. For example, Va is setto 90% of V0 or greater, and is preferably set to 95% of V0 or greater.When Va is excessively higher than V1, the difference in potential inadditional writing is easily recognized as the difference in luminance.Therefore, Va is set to V0 or less, or is set less than V0. For example,Va is preferably set to 99% of V0 or less.

In the example shown in FIG. 4, additional writing is performed once inthe second scan period S2. However, additional writing may be performeda plurality of times in the second scan period S2.

FIG. 5 shows another example of the timing chart for writing an imagesignal to the pixel PX comprising the pixel electrode PE1.

The example shown in FIG. 5 is different from that in FIG. 4 in respectthat additional writing is performed a plurality of times in the secondscan period S2 of one frame period T.

In a manner similar to that of the example of FIG. 4, one frame period Tcomprises the first scan period S1, the first hold period A, the secondscan period S2 and the second hold period B.

The first scan period S1 is equivalent to a period in which an imagesignal corresponding to the image to be displayed essentially is writtento all the pixels PX electrically connected to the gate line GL1. Theimage signal written to each pixel PX is retained in the first holdperiod A subsequent to the first scan period S1.

The second scan period S2 subsequent to the first hold period A isequivalent to a period in which an image signal is additionally writtento all the pixels PX electrically connected to the gate line GL1. A timelonger than the first scan period S1 is allocated to the second scanperiod S2. In the second scan period S2, the gate line GL1 is selected aplurality of times, and thus, additional writing is performed aplurality of times. In the example shown in the figure, additionalwriting is performed three times in the second scan period S2.

Specifically, the second scan period S2 includes a first period S21, asecond period S22 and a third period S23. The gate line GL1 is selectedby the gate driver GD in each of the first period S21, the second periodS22 and the third period S23. In the first to third periods S21 to S23,the switching elements connected to the gate line GL1 are conductive. Inthis manner, an image signal is supplied to the pixel electrode PE1 viathe switching elements which are in a conductive state. The image signalwritten to each pixel PX is retained in the second hold period Bsubsequent to the second scan period S2.

The first scan period S1 of the next frame period is equivalent to aperiod in which an image signal corresponding to the image to bedisplayed essentially is written to all the pixels PX electricallyconnected to the gate line GL1.

For example, the first scan period S1 is a period from the time pointwhen the pulse of the scan signal V(GL1) rises to the time point whenthe pulse falls. The first hold period A is equivalent to a period fromthe time point when the pulse of the scan signal V(GL1) falls in thefirst scan period S1 to the time point when the pulse of the scan signalV(GL1) rises in the first period S21 of the second scan period S2. Thesecond scan period S2 is equivalent to a period from the time point whenthe pulse of the scan signal V(GL1) rises in the first period S21 to thetime point when the pulse of the scan signal V(GL1) falls in the thirdperiod S23. The second hold period B is equivalent to a period from thetime point when the pulse of the scan signal V(GL1) falls in the thirdperiod S23 of the second scan period S2 to the time point when the pulseof the scan signal V(GL1) rises in the first scan period S1 of the nextframe period.

In this example, similarly, the first hold period A is set longer thanthe second hold period B. In one frame period T, the second scan periodS2 is close to the next frame period. In the example shown in thefigure, the second scan period S2 is started after the passage of a timelonger than T/2 from the start of the first scan period S1 (in otherwords, started in the latter half of the frame period T).

In the second scan period S2, the intervals of the first to thirdperiods S21 to S23 in which the gate line GL1 is selected are shorterthan the first hold period A. Specifically, an interval t12 between thefirst period S21 and the second period S22, and an interval t23 betweenthe second period S22 and the third period S23 are shorter than thefirst hold period A. Moreover, in some cases, the interval t12 and theinterval t23 may be shorter than the second hold period B. When sixtyframe periods are allocated to one second, the intervals t12 and t23 are1/60 s or greater. The length of the interval t12 may be the same as ordifferent from that of the interval t23.

Now, this specification explains the relationship of the image signalswhich are written in the second scan period S2 over a plurality oftimes.

When the difference in potential between the pixel electrode PE1 and thecommon electrode CE in the first scan period S1 (in other words, thepotential of the image signal written in the first scan period S1) isV0, and the difference in potential between the pixel electrode PE1 andthe common electrode CE in the first period S21 in which the gate lineGL1 is selected in the second scan period S2 (in other words, thepotential of the image signal additionally written in the first periodS21) is Va1, and the difference in potential between the pixel electrodePE1 and the common electrode CE in the second period S22 in which thegate line GL1 is selected again after the first period S21 in the secondscan period S2 (in other words, the potential of the image signaladditionally written in the second period S22) is Va2, the relationshipVa1≦Va2≦V0 is preferably satisfied.

When the difference in potential between the pixel electrode PE1 and thecommon electrode CE in the third period S23 in the second scan period S2(in other words, the potential of the image signal additionally writtenin the third period S23) is Va3, the relationship Va1≦Va2≦V3≦V0 ispreferably satisfied. Each of the potentials Va1 to Va3 of the imagesignal which is additionally written is set higher than the potentialV(PE1)=V1 of the pixel electrode PE1 at the time of the passage of thefirst hold period A.

When additional writing is performed a plurality of times in the secondscan period S2, Va1 to Va3 are preferably set so as to get close to thepotential V0 of the image signal written in the first scan period S1 ina stepwise manner relative to the reduced potential of the pixelelectrode PE at the time of passage of the first hold period A. Va1 toVa3 preferably satisfy the relationship V1<Va1<Va2<V3≦V0. By thissetting, the difference in potential in additional writing (for example,in the figure, the difference between the potentials V1 and Va1, thedifference between the potentials V2 and Va2, or the difference betweenthe potentials V3 and Va3) can be small. It is difficult to recognizethe difference in luminance which is caused by the difference inpotential. In this manner, the degradation of the display quality can beprevented.

FIG. 6 shows another example of the timing chart for writing an imagesignal to the pixel PX comprising the pixel electrode PE1.

The example shown in FIG. 6 is different from that in FIG. 5 in respectthat the second scan period S2 is started in the first half of one frameperiod. In other words, the second scan period S2 is started before thepassage of the period T/2 from the start of the first scan period S1.

In this example, similarly, the first hold period A is set longer thanthe second hold period B. By this setting, an effect similar to that ofthe example of FIG. 5 is obtained. Since the consumed power is increasedas the number of times of additional writing is increased, the number oftimes of additional writing in the second scan period S2 is preferablyten at a maximum when sixty frames are allocated to one second.

As explained above, according to the present embodiment, it is possibleto provide a display device which is capable of reducing the consumedpower and preventing the degradation of the display quality.

Some examples of other display devices which are obtained by thestructures disclosed in this specification are additionally describedbelow.

(1) A display device comprising:

a display panel comprising an active area; and

a driving portion which supplies a signal for displaying an image to thedisplay panel, wherein

the driving portion writes a first image signal to each pixel in a firstmain write period in which the active area is scanned,

the driving portion writes a second image signal to each pixel in anadditional write period in which the active area is scanned after thefirst main write period,

the driving portion writes a third image signal to each pixel in asecond main write period in which the active area is scanned after theadditional write period,

a first rest period in a non-scan state is provided between the firstmain write period and the additional write period, and a second restperiod in a non-scan state is provided between the additional writeperiod and the second main write period, and

the first rest period is longer than the second rest period.

(2) The display device of the above (1), wherein

a period from start of the main write period to start of the additionalwrite period is longer than a half of a frame period.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A display device comprising: a display panelincluding a gate line, a plurality of source lines intersecting with thegate line, and a plurality of switching elements electrically connectedto the gate line and the respective source lines; and a driving portionincluding a gate driver which selects the gate line by supplying apredetermined voltage to the gate line, and a source driver whichsupplies image signals to the source lines for each frame period,wherein the image signals are supplied from the connected source linesto pixel electrodes through the switching elements connected to the gateline selected by the gate driver, the frame period comprises a firstscan period in which the gate line is selected by the gate driver, afirst hold period subsequent to the first scan period, a second scanperiod in which the gate line is selected by the gate driver at leastonce subsequent to the first hold period, and a second hold periodsubsequent to the second scan period, the first hold period is longerthan the second hold period, and when a difference in potential betweenthe pixel electrode and a common electrode in the first scan period isV0, and a difference in potential between the pixel electrode and thecommon electrode at a time of passage of the first hold period is V1,and a difference in potential between the pixel electrode and the commonelectrode in the second scan period is Va, a relationship V1<Va≦V0 issatisfied, wherein V0, V1 and Va are real numbers.
 2. The display deviceof claim 1, wherein the first hold period is longer than a half of theframe period.
 3. The display device of claim 1, wherein the second scanperiod includes a first period in which the gate line is selected, and asecond period in which the gate line is selected again, and an intervalbetween the first period and the second period is shorter than the firsthold period.
 4. The display device of claim 1, wherein the V0 is greaterthan the Va.
 5. The display device of claim 4, wherein the Va is greaterthan or equal to 90% of the V0.
 6. The display device of claim 1,wherein when a difference in potential between the pixel electrode and acommon electrode in the first scan period is V0, and a difference inpotential between the pixel electrode and the common electrode in afirst period in which the gate line is selected in the second scanperiod is Va1, and a difference in potential between the pixel electrodeand the common electrode in a second period in which the gate line isselected again subsequent to the first period in the second scan periodis Va2, a relationship Va1≦Va2≦V0 is satisfied.